The present invention regards a row decoder for a nonvolatile memory with possibility of selectively biasing the word lines with positive or negative voltages.
As is known, nonvolatile memories comprise an array of cells arranged on rows and columns wherein word lines connect the gate terminals of the cells arranged on a same row, and bit lines connect the drain terminals of the cells arranged on a same column. Individual rows of the memory array are then addressed by a row decoder receiving at the input a coded address.
It is further known that, in a nonvolatile memory cell of the floating gate type, storage of a logic state is carried out by programming the threshold voltage of the memory cell so as to define the amount of electric charge stored in the floating gate region.
According to the stored information, memory cells may be distinguished into erased memory cells (stored logic state xe2x80x9c1xe2x80x9d), wherein no electric charge is stored in the floating gate region, and written or programmed memory cells (stored logic state xe2x80x9c0xe2x80x9d), wherein the electric charge stored in the floating gate region is sufficient to determine a sensible increase in the threshold voltage of the memory cells.
Erasing a nonvolatile memory is a highly complex operation, in that it entails a number of settings to be performed prior to proper erasing, when the electric charges present in the floating gate region is extracted and as a result the threshold voltage of the memory cells is reduced, and then entails verify operations and possibly further modifications after erasing when the result of erasing is not fully satisfactory.
In particular, to erase a sector, first of all a pre-conditioning operation is carried out, i.e., all the memory cells are brought to the programmed state regardless of their current state. Indeed, if a sector were erased wherein some of the memory cells are written but others have already been erased, during erasing there would be an over-erasing of the memory cells that have already been erased, so that these memory cells are very likely to become depleted, i.e., they have negative threshold voltage, and hence drain current even when their gate terminals are grounded. This effect proves particularly troublesome in that it simulates the constant presence of erased memory cells in the columns to which they belong, and thus all the memory cells belonging to these columns are read as being erased irrespective of their actual state.
In order to prevent this phenomenon and to render the history of all the memory cells belonging to the same sector uniform, writing of the entire sector is carried out.
Following upon the operation of pre-conditioning, all the memory cells of the sector are thus programmed and have threshold voltages with the distribution illustrated in FIG. 1 and identified with the binary information xe2x80x9c0xe2x80x9d associated to this distribution. For this distribution, FIG. 1 also shows the typical minimum values for the threshold voltages.
Next proper erasing is carried out. In this phase, for a so called xe2x80x9cnegative gatexe2x80x9d erasing, the drain and source terminals of the memory cells are appropriately biased in a per se known manner, and hence not described in detail, and an erase pulse typically having a duration of the order of 10 msec is applied on the gate terminals. Upon termination of the erase pulse, a verify operation is carried out on all the memory cells of the sector to check the value of their threshold voltages, and this verify operation is carried out by performing a marginal reading that will guarantee proper recognition of the memory cell in the normal read modality.
For this reason, erasing proceeds with applying an erase pulse followed by a verify operation until all the memory cells present a threshold voltage lower than a reference threshold voltage, the latter being the threshold voltage of the reference memory cell used during the verify operation.
At this point, all the memory cells of the sector have threshold voltages presenting the distribution illustrated in FIG. 1 and identified by the binary information xe2x80x9c1xe2x80x9d associated thereto, i.e., a distribution having a basically Gaussian form, in which the threshold voltage used during the verify operations referred to above is indicated by EV and is typically 2.5 V.
As may be noted from an analysis of FIG. 1, the distribution of the threshold voltages that is obtained after erasing has a form given by the superposition of a Gaussian curve and a tail due to the depleted memory cells.
Sector erasing cannot, however, be considered as yet concluded, because it is still necessary to ascertain whether there are depleted memory cells that may induce errors during reading.
Consequently, proper erasing is followed by a search phase for depleted memory cells, known as xe2x80x9csoft-programmingxe2x80x9d, including verifying the presence of a leakage current on the columns of the memory array, with all the rows of the array kept grounded.
When a column that presents this fault is identified, the first memory cell of the column is addressed, and a programming pulse having a preset amplitude is applied to the gate terminal to slightly shift the threshold of the memory cell, without, however, exceeding the EV value mentioned above. Next, reading of the second memory cell in the same column is carried out. If the memory cell has no leakage current, this means that the depleted memory cell was the previous one which has already been recovered; otherwise, programming of the memory cell in question is carried out, and so forth until the end of the column is reached.
Once the end of the column has been reached, verify is then repeated and, if there is still a leakage current present, the above described procedure is repeated, this time, however, increasing the amplitude of the programming pulse applied to the gate terminal of the memory cells during programming.
As may be noted from the above description, searching for depleted memory cells is particularly laborious and requires not only a non-negligible execution time, but also the supply of a considerable current when programming the depleted memory cells.
This latter aspect is of particular importance in memory devices with single supply voltage. In this case, in fact, all the necessary high voltages are obtained from the single supply voltage available through charge pumps, which present, however, a very limited current capacity, typically of just a few mA, and thus allowing only a small number of columns containing depleted memory cells to be simultaneously recovered.
A further drawback involved in the procedure of searching for depleted memory cells as described above is due to the fact that the illustrated problems, which are linked to the presence of a depleted memory cell in one column (simulation of the presence of an entirely erased column when in actual fact there are still memory cells having threshold voltages higher than EV) becomes particularly important and may even lead to jeopardizing the functioning of the memory in case of multilevel memory cells, i.e., memory cells that are each able to store more than one bit.
In fact, considering for example memory cells each containing two bits, the number of distributions of the threshold voltages is four, one for each combination of the logic levels of the pair of bits stored in a cell, instead of two as in case of conventional memory cells storing a single bit.
FIG. 2 illustrates the distributions of the threshold voltages deriving from the use of four level memory cells, i.e., cells storing two bits. For each distribution, the maximum and minimum values typical of the threshold voltages and the binary information associated thereto are indicated.
As may be noted from a comparison between FIG. 2 and FIG. 1, the latter regarding distributions resulting from the use of conventional two level memory cells, i.e., ones storing a single bit, the four distributions resulting from the use of multilevel memory cells fall within the same range of threshold voltage values in which the two distributions resulting from the use of conventional memory cells also fall, in that, for reasons of reliability it is not desirable to increase the voltage too much, and this consequently leads to a reduction in the distance between two adjacent distributions, and hence a reduction in the difference between the currents which flow in the memory cells and which correspond to adjacent levels.
Consequently, the introduction on the market of multilevel memory cells means that the margins of the distributions must be checked in an even more accurate way than with conventional memory cells, in so far as a multilevel memory cell which exceeds the threshold voltage EV (2.5 V) even by just a little could in fact be erroneously interpreted as belonging to the second distribution instead of to the first, thus possibly impairing the functioning of the memory.
One solution for considerably simplifying the search for depleted memory cells, directly identifying the depleted memory cells and reducing to the minimum all the above described problems, is that of biasing non-selected memory cells with negative voltages during verify. In this way, then, the leakage current during verify would be eliminated.
Such a solution is not, however, feasible using the row decoders known today. For a complete understanding of the limits of the currently known row decoders, which do not enable the use of such a solution, refer to FIG. 3, where the classic circuit diagram of a final decoding stage forming part of a row decoder (not illustrated) for a nonvolatile memory is illustrated.
In particular, the circuit diagram illustrated in FIG. 3 regards a final decoding stage used in a memory device allowing so-called xe2x80x9cnegative gate erasingxe2x80x9d, which envisages the application of a negative voltage to the gate terminals of the cells and of a positive voltage to the source terminals, with floating drain terminals.
As is shown in FIG. 3, the final decoding stage, indicated as a whole by 1, receives at the input a plurality of pre-decoding signals Lx, Ly, Lz, P, generated by a pre-decoding stage (not illustrated), which also is part of the row decoder arranged upstream of the final decoding stage and generating the above decoding signals according to the addresses of the memory location to be addressed. The final decoding stage 1 has the purpose of biasing a word line of the memory array 2 made up of a plurality of cells 3, arranged in rows and columns, wherein the word lines (only two of which, for reasons of simplicity of illustration are shown in FIG. 3, indicated by WL less than i greater than  and WL less than i+1 greater than ) connect the gate terminals of the memory cells 3 arranged on a same row, and the bit lines (not illustrated) connect the drain terminals of the memory cells 3 arranged on a same column.
In particular, the pre-decoding signals Lx, Ly and Lz are used to select the group of word lines, typically 8 or 16, biased through the final decoding stage 1, while the pre-decoding signals P are used to select a single word line within the group.
The final decoding stage 1 comprises a first supply line 4 set at a voltage VPC, which during cell addressing is equal to a supply voltage VCC (typically, of between 2.5 and 3.5 V), and during cell programming is equal to the programming voltage VPPhigher than the supply voltage VCC (for example, 12 V); and a second supply line 5 set at a voltage VNEG, which, during reading and programming of the memory cells, is equal to a ground voltage VGND (for example, 0 V), and during memory cell erasing is equal to an erase voltage VERN lower than ground voltage VGND (for example, xe2x88x928 V).
The final decoding stage 1 further comprises an input selection circuit 6 formed by a NAND logic gate receiving as input the pre-decoding signals Lx, Ly, Lz and supplying as output a block selection signal SB; a plurality of output driver circuits 8 of the latch type, one for each word line addressable through the final decoding stage 1, which generate at the output biasing signals R less than i greater than , R less than i+1 greater than  for respective word lines WL less than i greater than , WL less than i+1 greater than ; and a plurality of switching circuits 10, one for each word line addressable through the final decoding stage 1, each of which circuits is arranged between the output of the selection circuit 6 and the input of a respective driver circuit 8, receives at the input a respective pre-decoding signal P less than i greater than , P less than i+1 greater than , and has the purpose of selectively interrupting the connection between the selection circuit 6 and the respective driver circuit 8 according to the respective pre-decoding signal P less than i greater than , P less than i+1 greater than .
The pre-decoding signals Lx, Ly, Lz, and P, as well as the block selection signal SB are logic signals having a low logic state defined by the ground voltage VGND and a high logic state defined by the supply voltage VCC.
Each driver circuit 8 comprises an inverter 12 comprising a pull-up PMOS transistor 14 and a pull-down NMOS transistor 16 having gate terminals connected together and defining an input node 18, drain terminals connected together and defining an output node 20 on which the respective biasing signal R less than i greater than , R less than i+1 greater than  is present, and source and bulk terminals connected to the first and, respectively, the second supply lines 4, 5.
Each driver circuit 8 further comprises a feedback PMOS transistor 28 having its gate terminal connected to the output node 20, its drain terminal connected to the input node 18, and its source and bulk terminals connected to the first supply line 4.
The NMOS transistors 16 have a triple-well type structure, as shown in FIG. 4; i.e., they present a bulk region made in a P-type well 22 set at the voltage VNEG and formed in an N-type well 24 set at the supply voltage VCC and in turn formed in a substrate 26 which is set at the ground voltage VGND. In this way, the P-type well 22 is electrically isolated from the substrate 26 and thus enables biasing of the bulk regions of the transistors 16 at a potential, in the case in point VNEG, different from the potential of the substrate 26 (ground voltage VGND).
Each switching circuit 10 comprises a first NMOS pass transistor 30 and a second NMOS pass transistor 32 arranged in series and coupled between the output terminal of the NAND logic gate and the input node 18 of the respective driver circuit 8. In particular, the NMOS transistor 30 has its drain terminal connected to the output terminal of the NAND logic gate, its gate terminal set at the supply voltage VCC, and its source terminal connected to the drain terminal of the NMOS transistor 32, which in turn has its gate terminal receiving the respective pre-decoding signal P less than i greater than , P less than i+1 greater than , and its source terminal connected to the output node 18.
Negative gate erasing is an intrinsically non-selective operation and is carried out in a known way, and thus not described in detail herein, first of all biasing the second supply line 5 at the erase voltage VERN and then deselecting all the word lines WL less than i greater than , WL less than i+1 greater than . In this way, the input nodes 18 are set at a high logic level, and hence the NMOS transistors 16 are on, thus connecting the output nodes 20 to the second supply line 5, and consequently determining application of the erase voltage VERN to the word lines WL less than i greater than , WL less than i+1 greater than .
To search for depleted memory cells in the way described previously, it is necessary to selectively bias the word lines, and in particular it is necessary to apply a positive verify voltage to a single word line at a time, and a negative voltage to all the other word lines.
A selective biasing of this sort is not, however, possible with the final decoding stage described above. In fact if the attempt were made to apply a positive voltage to one word line and a negative voltage to all the other word lines, the input nodes 18 of the biasing circuits 8 of the non-selected word lines, and hence the gate terminals of the NMOS transistors 16, would all be set at the voltage VPC, whilst the source terminals of these transistors would be set at the erase voltage VERN. Consequently, the corresponding NMOS transistors 16 would all be turned on and would connect the respective word lines to the second supply line 5 set at the erase voltage VERN.
On the other hand, the input node 18 of the driver circuit 8 of the selected word line, and hence the gate terminal of the respective NMOS transistor 16, would be set at the ground voltage VGND defined by the low logic level assumed by the block selection signal SB, while the source terminal of this NMOS transistor 16 would be set at the erase voltage VERN lower than the ground voltage VGND. Consequently, the PMOS transistor 14 would be on, while the NMOS transistor 16 would be off.
If, however, the difference between the ground voltage VGND and the erase voltage VERN is higher than the threshold voltage of the NMOS transistor 16, also this transistor will be on and, jointly with the PMOS transistor 14, which is on, will connect together the first and the second supply lines 4, 5, thus preventing proper biasing of the respective word line, and consequently jeopardizing the reliability of searching for depleted memory cells.
A solution for overcoming the above described problem without modifying the circuit structure of the final decoding stage includes using NMOS transistors 16 having a threshold voltage higher than the difference between the ground voltage VGND and the erase voltage VERN.
If not directly available with such characteristics, transistors of the sort could be obtained by suitably biasing the bulk regions 22 so as to increase the threshold voltage of these transistors, exploiting the well known body effect.
Even if this solution presents a greater circuit simplicity because the circuit structure of the final decoding stage does not need to be modified, it entails a greater complexity for managing the various voltages necessary during word line decoding. Biasing a substrate means, in fact, charging and discharging large parasitic capacitances, and, in addition, the times for charging and discharging must be well controlled in order to prevent direct biasing of the junctions. Furthermore, a solution of this type imposes a limit on the erase voltage VERN used during verify.
The purpose of the present invention is therefore that of providing a word line decoder that enables selective biasing of the word lines with positive or negative voltages.
According to the present invention, a word line decoder for a nonvolatile memory with the possibility of selectively biasing the word lines with positive or negative voltages is provided.